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Carmi Merimovich

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x86-32 pae basic mmu doc

cr3

The external table must be page aligned. Loading of CR3 purges the TLB unless we have ASIDs in the TLB.

External Page Table Entry

An entry in the external table has the following format:

For our purpose only the rightmost three bits are of importance. In fact only the P bit is relevant since the page size we use is always 4KB and both the U and R bit are always one.

Middle Page Table Entry

An entry in the middle table has the following format:

For our purpose only the rightmost three bits are of importance. In fact only the P bit is relevant since the page size we use is always 4KB and both the U and R bit are always one.

Internal Page Table Entry

The internal table entries are almost identical to the external table entries. For our purpose the entries are identical.

The same comment noted for the external page table entries is also relevant here, i.e., only the rightmost three bits are of importance. In fact only the P bit is relevant since e page size we use is always 4KB and both the U and R bit are always one.

Virtual Address

The virtual address is considered to have three fields as follows.

References

The definite information on paging on Intel's processsor can be find in reference 1 chapter 4. Reference 2 has good information in condensed form.